This invention relates to a signal level-comparing circuit.
In general, in an LSI circuit formed of MOS transistors, the voltage level of an input signal to the LSI circuit is chosen to fall within the range defined by the power source voltage of the LSI circuit. Assuming that the power source voltage VDD has 5 volts, the voltage or dynamic range of an input signal to the above-mentioned LSI circuit is defined within the range of 0 to 5 volts. This means that when the voltage of an output signal from the LSI circuit is changed from a high level to a low level or vice versa, the level of the correspondingly input signal to the LSI circuit is supposed to be set between 0 and 5 volts. When the ordinary CMOS inverter is supplied with, for example, an input signal shown in FIG. 1A, then an output signal indicated in FIG. 1B is produced. When, in this case, the input signal reaches a prescribed level, the output signal is inverted. In a case where an ordinary Schmitt trigger circuit is supplied with an input signal shown in FIG. 2A, then an output signal indicated in FIG. 2B is obtained. When, in this case, the voltage level of an input signal becomes higher than a first prescribed voltage level, then the resultant output signal has its voltage changed from a lower to a high level. Conversely when an input signal has its voltage set at a second prescribed level lower than the first prescribed voltage level, then the output signal has its voltage shifted from a high to a low level.
No problems have been raised, so long as the CMOS inverter, Schmitt trigger, etc. are supplied, for example, with an input signal having a lower voltage than the power source voltage. However, as a microcomputer, for example, is applied in a progressively wider field, it is more strongly demanded to process an input signal whose maximum voltage stands higher than the voltage for operating an LSI device constituting the microcomputer. In other words, a strong demand is made to develop a circuit which, when an input signal has a voltage level lying between the voltages VSS and VDD shown in FIG. 3A, sends forth an output signal having a voltage level VDD indicated in FIG. 3B, and when an input signal has a voltage level higher than a prescribed level set between the power source voltage VDD and maximum voltage VHH, produces an output signal having a voltage level of VSS shown in FIG. 3B.